Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits

ABSTRACT

A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.

BACKGROUND Field

Aspects of the present disclosure relate generally to memory circuits,and in particular, to an apparatus and method for implementing designfor testability (DFT) for bitline drivers of memory circuits.

Background

A memory circuit typically includes a two-dimensional array of memorycells. Memory cells common to rows (or columns) are coupled to a set ofwordlines, respectively. Memory cells common to columns (or rows) arecoupled to a set of complementary bitlines, respectively.

The memory circuit typically includes a wordline driver for selectingtarget memory cells upon which a data write or read operation will beperformed. The wordline driver performs this selection by generating anasserted signal on the wordline coupled to the target memory cells, andgenerating deasserted signals on the remaining wordlines of the set. Theasserted signal on the wordline causes the target memory cells to becoupled to complementary bitlines, respectively.

For reading data from the memory array, the memory circuit includes asense amplifier coupled to the set of complementary bitlines. When thewordline driver selects a row (or column) of target memory cells forreading data therefrom, the sense amplifier senses the data on thecomplementary bitlines. The sense amplifier then reads out the data andprovides it to a data output port.

For writing data into the memory array, the memory circuit includes aset of bitline drivers for generating data signals on the complementarybitlines for writing data into target memory cells, respectively. Eachbitline driver of the set includes a data input port for receiving adata signal for writing data to the target memory cell. Each bitlinedriver of the set includes a write mask input port for receiving a writemask signal for masking the writing of data to a memory cell even if adata signal is present at the data input port.

This disclosure pertains to bitline drivers for improved functional andtest mode operations.

SUMMARY

The following presents a simplified summary of one or more embodimentsin order to provide a basic understanding of such embodiments. Thissummary is not an extensive overview of all contemplated embodiments,and is intended to neither identify key or critical elements of allembodiments nor delineate the scope of any or all embodiments. Its solepurpose is to present some concepts of one or more embodiments in asimplified form as a prelude to the more detailed description that ispresented later.

An aspect of the disclosure relates to an apparatus including a firstlatch configured to latch a data signal in response to a first state ofa clock signal if a scan shift signal is deasserted, and latch a testvector signal in response to the first state of the clock signal if thescan shift signal is asserted; and a second latch configured to latch awrite mask signal in response to the first state of the clock signal ifthe scan shift signal is deasserted, and latch the test vector signal inresponse to the first state of the clock signal if the scan shift signalis asserted.

Another aspect of the disclosure relates to a method including latchinga data signal at a first node in response to a first state of a clocksignal if a scan shift signal is deasserted; latching a test vectorsignal at the first node in response to the first state of the clocksignal if the scan shift signal is asserted; latching a write masksignal at a second node in response to the first state of the clocksignal if the scan shift signal is deasserted; and latching the testvector signal at the second node in response to the first state of theclock signal if the scan shift signal is asserted.

Another aspect of the disclosure relates to an apparatus including afirst latch configured to latch a data signal in response to a firststate of a clock signal if a write mask signal and a scan shift signalare deasserted, and latch a test vector signal in response to the firststate of the clock signal if the scan shift signal is asserted; and asecond latch configured to latch the test vector signal from the firstlatch in response to a second state of the clock signal if the scanshift signal is asserted.

Another aspect of the disclosure relates to a method including latchinga data signal at a first node in response to a first state of a clocksignal if a write mask signal and a scan shift signal are deasserted;latching a test vector signal at the first node in response to the firststate of the clock signal if the scan shift signal is asserted; andlatching the test vector signal at a second node in response to a secondstate of the clock signal if the scan shift signal is asserted.

To the accomplishment of the foregoing and related ends, the one or moreembodiments include the features hereinafter fully described andparticularly pointed out in the claims. The following description andthe annexed drawings set forth in detail certain illustrative aspects ofthe one or more embodiments. These aspects are indicative, however, ofbut a few of the various ways in which the principles of variousembodiments may be employed and the description embodiments are intendedto include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a block diagram of an exemplary memory circuit inaccordance with an aspect of the disclosure.

FIG. 1B illustrates a schematic diagram of an exemplary memory cell andprecharge circuit in accordance with another aspect of the disclosure.

FIG. 2 illustrates a schematic diagram of an exemplary bitline driver inaccordance with another aspect of the disclosure.

FIG. 3 illustrates a schematic diagram of another exemplary bitlinedriver in accordance with another aspect of the disclosure.

FIG. 4 illustrates a schematic diagram of another exemplary bitlinedriver in accordance with another aspect of the disclosure.

FIG. 5 illustrates a flow diagram of an exemplary method of operating abitline driver in accordance with another aspect of the disclosure.

FIG. 6 illustrates a flow diagram of another exemplary method ofoperating a bitline driver in accordance with another aspect of thedisclosure.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with theappended drawings, is intended as a description of variousconfigurations and is not intended to represent the only configurationsin which the concepts described herein may be practiced. The detaileddescription includes specific details for the purpose of providing athorough understanding of the various concepts. However, it will beapparent to those skilled in the art that these concepts may bepracticed without these specific details. In some instances, well-knownstructures and components are shown in block diagram form in order toavoid obscuring such concepts.

FIG. 1A illustrates a block diagram of an exemplary memory circuit 100in accordance with an aspect of the disclosure. The memory circuit 100includes a memory array 110 of memory cells (C). In this example, thememory array 110 is configured as a two-dimensional array having adimension of (n+1) by (m+1) memory cells (C). As discussed furtherherein, each memory cell (C) may be configured as a static random accessmemory (SRAM) type memory cell, or other type of memory cell.

The memory circuit 100 further includes a word line (WL) controller 120for generating asserted signals on a set of wordlines WL_0 to WL_m basedon a control signal wl_cntl for accessing one or more memory cells (C)coupled to the asserted wordlines, respectively. As illustrated, thewordlines WL_0 to WL_m are coupled to columns of memory cells (C),respectively.

The memory circuit 100 further includes a set of bitline drivers 0 to nfor generating complementary signals for writing data into rows ofmemory cells (C) coupled to complementary bitlines BL_0/BL_0 toBL_n/BL_n, respectively. The bitline drivers 0 to n include data inputports din_0 to din_n for receiving data for writing data to memory cells(C) coupled to the corresponding bitlines BL_0/BL_0 to BL_n/BL_n,respectively. The bitline drivers 0 to n include write mask input portswbt_0 to wbt_n for receiving write mask signals for masking the writingof data to memory cells (C) coupled to bitlines BL_0/BL_0 to BL_n/BL_n,respectively.

In order to implement design for testability (DFT) for testing theoperation of the bitline drivers 0 to n, the bitline driver 0 includes ascan input port sin_0 for receiving a test vector signal from anexternal test equipment, and the bitline driver n includes a scan outputport sou_n for outputting a captured test vector signal to the externaltest equipment. The scan path is routed from the scan input port sin_0to the scan output sou_n consecutively via all of the bit line drivers 0to n. For instance, as illustrated, the bitline driver 0 includes a scanoutput port sou_0 coupled to the scan input port sin_1 of bitline driver1. Similarly, the bitline driver n−1 includes a scan output port sou_n−1coupled to the scan input port sin_n of bitline driver n.

In general, for any intermediate bitline driver (where its positionindex k in the chain is not 0 or n), the k^(th) bitline driver includesa scan input port sin_k coupled to the scan output port sin_k−1 of thek^(th)−1 bitline driver, and a scan output port sou_k coupled to thescan input port sin_k+1 of the k^(th)+1 bitline driver.

For reading data from the memory array 110, the memory circuit 100further includes a sense amplifier 130 including a set of complementaryinputs coupled to the set of complementary bitlines BL_0/BL_0 toBL_n/BL_n, respectively. The sense amplifier 130 further includesanother input for receiving a control signal bl_cntl for enabling thereading of data from the memory cells (C). Additionally, the senseamplifier 130 includes a data output port dout for outputting the readdata.

For controlling the writing and reading of data to and from the memoryarray 110 and the testing the bitline drivers 0 to n, the memory circuit100 further includes a memory controller 140. The memory controller 140includes: an input for receiving data to be written into the memoryarray 110; an input for receiving an address signal for identifyingtarget memory cells (C) of the memory array 110 to or from which data isto be written or read; an input for receiving a read/write (R/W) controlsignal for specifying whether the current memory operation is a read orwrite operation; and an input for receiving a test signal for operatingthe bitline drivers 0 to n in test mode.

In response to the aforementioned inputs, the memory controller 140generates data signals din< > (din_0 to din_n) and write mask signalswbt< > (wbt_0 to wbt_n) for the bitline drivers 0 to n, wl_cntl controlsignal for the wordline (WL) controller 120, bl_cntl control signal forthe sense amplifier 130, and shift and clock (clk) signals for thebitline drivers 0 to n, as discussed in more detail herein.

The writing of data into memory circuit 100 may operate as follows: Inthis example, the writing of data into one or more memory cells (C)coupled to wordline WL_0 is discussed. It shall be understood that thewriting of data into one or more memory cells (C) coupled to otherwordlines operates in a similar manner.

For instance, if data is to be written into all of the memory cells (C)coupled to wordline WL_0, the corresponding write mask signals wbt_0 towbt_n are deasserted (e.g., at a logic zero (0) voltage level) so thatthe writing of data to the memory cells (C) is not masked. Theparticular data to be written into the memory cells (C) are applied tothe data input ports din_0 to din_n. Additionally, based on the controlsignal wl_cntl, the WL controller 120 generates an asserted signal onthe wordline WL_0 to couple the corresponding memory cells to thebitlines BL_0/BL_0 to BL_n/BL_n (and generates deasserted signals on allremaining wordlines WL_1 to WL_m so that the corresponding memory cellsare not coupled to bitlines BL_0/BL_0 to BL_n/BL_n). Based on thedeasserted mask signals wbt_0 to wbt_n and the input data signals din_0to din_n, the bit line drivers 0 to n write the corresponding data intothe memory cells (C).

For example, if a logic one (1) is to be written into the memory cell(C) coupled to the wordline WL_0 and complementary bitlines BL_0/BL_0 ,the wordline (WL) controller 120 generates an asserted signal (e.g., ata logic one (1) voltage level) on the wordline WL_0 (and generatesdeasserted signals (e.g., at logic zero (0) voltage levels) on theremaining wordlines WL_1 to WL_m), and the bitline driver 0 generates alogic one (1) voltage level on bitline BL_0 and a logic zero (0) voltagelevel on complementary bitline BL_0 . If a logic zero (0) is to bewritten into the same memory cell (C), the wordline (WL) controller 120generates the same asserted and deasserted signals, and the bitlinedriver 0 generates a logic zero (0) voltage level on bitline BL_0 and alogic one (1) voltage level on complementary bitline BL_0 .

If the writing of data into one or more memory cells coupled to thebitlines BL_0/BL_0 to BL_n/BL_n is to be masked or suppressed (eventhough the data signal is present in the corresponding data inputport(s)), the corresponding mask signal(s) is/are asserted (e.g., at alogic one (1) voltage level).

The reading of data from memory circuit 100 may operate as follows: Inthis example, the reading of data from memory cells (C) coupled towordline WL_0 is discussed. It shall be understood that the reading ofdata from memory cells (C) coupled to other word lines operates in asimilar manner.

The sense amplifier 130 precharges the complementary bitlines BL_0/BL_0to BL_n/BL_n with a high logic voltage based on the bl_cntl controlsignal. Based on the control signal wl_cntl indicating that the memorycells (C) coupled to wordline WL_0 is to be read, the WL controller 120generates an asserted signal on the wordline WL_0 to couple thecorresponding memory cells to the bitlines BL_0/BL_0 to BL_n/BL_n (andgenerates deasserted signals on all remaining wordlines WL_1 to WL_m sothat the corresponding memory cells are not coupled to bitlinesBL_0/BL_0 to BL_n/BL_n. The precharged complementary bitlines BL_0/BL_0to BL_n/BL_n change logic states depending on the data stored by thecorresponding memory cells (C). The sense amplifier 130 senses the logicstates on the complementary bitlines BL_0/BL_0 to BL_n/BL_n to read outand produce the data at the data output port dout.

The testing of the bitlines drivers may operate as follows: In responseto the test signal indicating a scan shift test mode, the memorycontroller 140 generates an asserted scan shift signal (e.g., at a highlogic voltage). A test vector signal from an external test equipment(not shown) is applied to the scan input sin_0 of the bitline driver 0.And, the memory controller 140 generates a clock signal clk at arelatively low frequency (e.g., shift mode frequency) to accuratelycause the test vector signal to propagate from bitline driver 0 tobitline driver n.

In response to the test signal indicating a scan capture test mode, thememory controller 140 generates a deasserted scan shift signal (e.g., ata low logic voltage) and generates the clock signal (clk) at arelatively high frequency (e.g., functional mode frequency or frequencyat which latches of the bitline driver will be tested). The test vectorsignal is then captured by the corresponding latches of the bitlinedrivers 0 to n.

Then, in response to the test signal again indicating a scan shifttesting mode, the memory controller 140 generates the asserted scanshift signal and the clock signal clk at the relatively low frequency(e.g., shift mode frequency) to accurately shift out the captured testvector signal from the bitline drivers 0 to n to the external testequipment via the scan output port sou_n of bitline driver n. Based onthe input test vector signal and the captured test vector signal, thetest equipment is able to determine operational errors in the bitlinedrivers 0 to n.

FIG. 1B illustrates a schematic diagram of an exemplary memory cell 150and a corresponding precharge circuit 160 in accordance with anotheraspect of the disclosure. As discussed above, each memory cell (C) ofthe memory circuit 100 may be configured as an SRAM type memory cell. Inthis example, the memory cell 150 is coupled to the j^(th) wordline WL_jand the k^(th) complementary bitlines BL_k/BL_k.

Accordingly, the memory cell 150 includes a first inverter having ap-channel metal oxide semiconductor (PMOS) field effect transistor (FET)M1 coupled in series with an n-channel metal oxide semiconductor (NMOS)FET M2 between an upper voltage rail (VDD) and a lower voltage rail(e.g., ground). The memory cell 150 further includes a second inverterincluding a PMOS FET M3 coupled in series with an NMOS FET M4 betweenthe upper voltage rail (VDD) and the lower voltage rail (ground).

The first and second inverters are cross-coupled. That is, the output ofthe first inverter (at the drains of FETs M1 and M2) is coupled to theinput (at the gates of FETs M3 and M4) of the second inverter, and theoutput of the second inverter (at the drains of FETs M3 and M4) iscoupled to an input (at the gates of FETs M1 and M2) of the firstinverter.

The memory cell 150 further includes access NMOS FETs M5 and M6 withgates coupled to the corresponding wordline WL_j, drain/source coupledto the complementary bitlines BL_k/BL_k, and source/drain coupled to theoutputs of the first and second inverters, respectively. As noted by theellipsis above and below the memory cell 150, other similarly structuredmemory cells are coupled to the complementary bitlines BL_k/BL_k.

As mentioned above, each pair of complementary bitlines BL_k/BL_kincludes a corresponding precharge circuit 160 for precharging thebitlines pursuant to a read operation. In this example, the prechargecircuit 160 includes a PMOS FET M7 coupled between the upper voltagerail (VDD) and bitline BL_k; a PMOS FET M8 coupled between the uppervoltage rail (VDD) and complementary bitline BL_k; and a PMOS FET M9coupled between the complementary bitlines BL_k/BL_k.

The sense amplifier 130 generates an asserted precharge signal (pre)(e.g., at a low logic voltage level) in order to precharge thecomplementary bitlines BL_k/BL_k pursuant to a read operation. That is,the asserted precharge signal (pre) turns on FETs M7, M8, and M9 tocouple the upper voltage rail (VDD) to the complementary bitlinesBL_k/BL_k to effectuate their precharging. After the bitlines BL_k/BL_khas been precharged, the precharge signal (pre) is deasserted to turnoff the FETs M7, M8, and M9 and decouple the upper voltage rail (VDD)from the bitlines BL_k/BL_k.

FIG. 2 illustrates a schematic diagram of an exemplary bitline driver200 in accordance with another aspect of the disclosure. The bitlinedriver 200 may be an example of one of the bitline drivers 0 to n ofmemory circuit 100 previously discussed. For instance, the bitline drive200 may be the k^(th) bitline driver of the bitline drivers 0 to n.

In particular, the bit line driver 200 includes a multiplexer 210 withtristate inverters I₁, I₂, and I₈ (generally, gating devices); a firstmaster-latch 220 including a pass gate PG₁, inverter I₃ and tristateinverter I₄; a first slave-latch 230 including a pass gate PG₂, inverterI₅ and tristate inverter I₆; tristate inverter I₇; a second master-latch240 including a pass gate PG₃, inverter I₉ and tristate inverter I₁₀;and a second slave-latch 250 including a pass gate PG₄, inverter I₁₁ andtristate inverter I₁₂. The bit line driver 200 further includes a datawrite circuit 260 including first and second NOR-gates NG₁ and NG₂,inverters I₁₃ and I₁₄, and pass gates PG₅ and PG₆ coupled tocomplementary bitlines BL_k/BL_k. A column of memory cells (C) and acorresponding precharge circuit (both not shown in FIG. 2) are coupledto complementary bitline BL_k/BL_k, as previously discussed with respectto FIG. 1.

The tristate inverter I₁ of the multiplexer 210 includes an inputcoupled to a scan input port sin_k for receiving a test vector signal.The scan input port sin_k is coupled to the scan output sou_k−1 of thek^(th)−1 bit line driver if it is not bitline driver 0 or to an externalinput port if it is bitline driver 0. The tristate inverter I₁ isenabled (outputs an inverted input signal) and disabled (produces atristated output) based on complementary shift signals ishift/ishift(e.g., enabled if ishift=1 and ishift=0, and disabled if ishift=0 andishift=1).

The tristate inverter I₂ of the multiplexer 210 includes an inputcoupled to the write mask port wbt_k. The tristate inverter I₂ isenabled and disabled based on complementary shift signals ishift/ishift(e.g., enabled if ishift=0 and ishift=1, and disabled if ishift=1 andishift=0). The outputs of the tristate inverters I₁ and I₂ are coupledtogether and to an input of the first master-latch 220 (in particularly,to the input of the pass gate PG₁).

The pass gate PG₁ of the master-latch 220 is enabled (passes its inputsignal) and disabled (does not pass its input signal) based oncomplementary clock signals clk/clk (e.g., enabled if clk=0 and clk=1,and disabled if clk=1 and clk=0). The output of the pass gate PG₁ iscoupled to the input and output of inverters I₃ and I₄ of themaster-latch 220, respectively. The inverters I₃ and I₄ (serving as thelatch mechanism of the master-latch 220) are enabled (cross-coupled forlatching signal) and disabled (not cross-coupled for not latchingsignal) based on complementary clock signals clk/clk (e.g., enabled ifclk=1 and clk=0, and disabled if clk=0 and clk=1). The output of thefirst master-latch 220 (at the input and output of inverters I₄ and I₃,respectively) is coupled to an input of the first slave-latch 230 (inparticularly, to the input of pass gate PG₂) and respective first inputsof NOR-gates NG₁ and NG₂ of the data write circuit 260.

The second pass gate PG₂ of the first slave-latch 230 is enabled anddisabled based on complementary clock signals clk/clk (e.g., enabled ifclk=1 and clk=0, and disabled if clk=0 and clk=1). The output of thesecond pass gate PG₂ is coupled to input and output of inverters I₅ andI₆, respectively. The inverters I₅ and I₆ (serving as the latchmechanism of the slave-latch 243) are enabled and disabled based oncomplementary clock signals clk/clk (e.g., enabled if clk=0 and clk=1,and disabled if clk=1 and clk=0). The output of the first slave-latch230 (at the input and output of inverters I₆ and I₅, respectively) iscoupled to an input of tristate inverter I₇.

The tristate inverter I₇ is enabled and disabled based on complementaryshift signals ishift/ishift (e.g., enabled if ishift=1 and ishift=0, anddisabled if ishift=0 and ishift=1). The output of the tristate inverterI₇ is coupled to an input of the second master-latch 240 (inparticularly, to the input of pass gate PG₃).

The other tristate inverter I₈ of the multiplexer 210 includes an inputcoupled to the data input port din_k. The tristate inverter I₈ isenabled and disabled based on complementary shift signals ishift/ishift(e.g., enabled if ishift=0 and ishift=1, and disabled if ishift=1 andishift=0). The output of the tristate inverter I₈ is also coupled to theinput of the second master-latch 240 (in particularly, to the input ofthe third pass gate PG₃).

The pass gate PG₃ of the second master-latch 240 is enabled and disabledbased on complementary clock signals clk/clk (e.g., enabled if clk=0 andclk=1, and disabled if clk=1 and clk=0). The output of the pass gate PG₃is coupled to input and output of inverters I₉ and I₁₀ of the secondmaster-latch 240, respectively, and a second input of NOR-gate NG₂ ofthe data write circuit 260. The inverters I₉ and I₁₀ (operating as thelatch mechanism of the second master-latch 240) are enabled and disabledbased on complementary clock signals clk/clk (e.g., enabled if clk=1 andclk=0, and disabled if clk=0 and clk=1). The output of the secondmaster-latch 240 (at the input and output of inverters I₁₀ and I₉,respectively) is coupled to an input of the second slave-latch 250 (inparticularly, to an input of the pass gate PG₄) and a second input ofNOR-gate NG₁ of the data write circuit 260.

The pass gate PG₄ of the second slave-latch 250 is enabled and disabledbased on complementary clock signals clk/clk (e.g., enabled if clk=1 andclk=0, and disabled if clk=0 and clk=1). The output of the pass gate PG₄is coupled to input and output of the inverters I₁₁ and I₁₂ (operatingas the latch mechanism of the second slave-latch 250), respectively. Theinverters I₁₁ and I₁₂ are enabled and disabled based on complementaryclock signals clk/clk (e.g., enabled if clk=0 and clk=1, and disabled ifclk=1 and clk=0).

The output of the second slave-latch 250 (at the input and output ofinverters I₁₁ and I₁₂, respectively) is coupled to the scan output portsou_k of the bit line driver 200. The scan output port sou_k is coupledto the scan input port sin_k+1 of the k^(th)+1 bitline driver if it isnot bitline driver n or to an external output port if it is bitlinedriver n.

With regard to the data write circuit 260, the outputs of the NOR-gatesNG₁ and NG₂ are coupled to inputs of inverters I₁₃ and I₁₄,respectively. The outputs of the inverters I₁₃ and I₁₄ are coupled toinputs of pass gates PG₅ and PG₆, respectively. The pass gates PG₅ andPG₆ may be controlled by complementary bitline select signals wm/wm. Thepass gates PG₅ and PG₆ are enabled if the wm/wm signals are high/low,and disabled if the wm/wm signals are low/high. The outputs of the passgates PG₅ and PG₆ are coupled to the complementary bitlines BL_k/BL_k,respectively.

The following describes the writing of data to (as well as masking thewriting of data from) a memory cell coupled to the complementarybitlines BL_k/BL_k in functional mode (e.g., non-test mode). Infunctional mode, the complementary shift signals ishift/ishift are logiczero (0) and logic one (1), respectively. Accordingly, the inverters andI₇ are disabled or tristated. In functional mode, the slave-latches 230and 250 and inverter I₇ serve no function. Additionally, in functionalmode, the tristated inverters I₂ and I₈ are enabled.

To distinguish signals from ports, signals will be represented with anitalicized font and corresponding ports with non-italicized font.Further, signals may be inverted and reinverted as they are processed bythe bitline driver 200, but are, nonetheless, the same signals whetherthey are in the inverted domain or non-inverted domain.

During a first half clock cycle when the complementary clock signalsclk/clk are low/high, the write mask signal wbt_k is routed from thewrite mask port wbt_k to the input of inverter I₃ by the tristateinverter I₂ and the pass gate PG₁. Also, during the first half clockcycle, the input data signal din_k is routed from the data input portdin_k to the input of the inverter I₉ and the second input of theNOR-gate NG₂ by the tristate inverter I₈ and the pass gate PG₃.

During a second half clock cycle when the complementary clock signalsclk/clk are high/low, the pass gates PG₁ and PG₃ are disabled to preventany signal or noise on the ports wbt_k and data din_k from affecting thelatching of the write mask signal wbt_k and the data signal din_k by theenabled inverters I₃/I₄ and I₉/I₁₀, respectively. During the second halfclock cycle, the first master-latch 220 latches the write mask signalwbt_k, and the second master-latch 240 latches the data signal din_k.

The latched write mask signal wbt_k is applied to the respective firstinputs of the NOR-gates NG₁ and NG₂ of the data write circuit 260. Theunlatched and inverted data signal data signal din_k is applied to thesecond input of the NOR-gate NG₁, and the latched and non-inverted datasignal din_k is applied to the second input of the NOR-gate NG₂.

If the write mask signal wbt_k is asserted (e.g., at a logic one (1)) tomask the writing of data into a memory cell (C), the NOR-gates NG₁ andNG₂ output logic low states. In response, the inverters I₁₃ and I₁₄generate logic high states. The logic high states are produced on thecomplementary bitlines BL_k/BL_k via the pass gates PG₅ and PG₆, whichare enabled via the bitline select signals wm/wm during a writeoperation. The logic high states on the complementary bitlines BL_k/BL_kprevent the changing of data stored by the memory cell (C) enabled bythe asserted wordline.

If the write mask signal wbt_k is deasserted (e.g., at a logic zero (0))so as not to mask the writing of data into a target memory cell (C), theNOR-gates NG₁ and NG₂ output the inverted and non-inverted data signaldin_k. In response, the inverters I₁₃ and I₁₄ output the non-invertedand inverted data signal din_k. The non-inverted and inverted datasignal din_k is applied to complementary bitlines BL_k/BL_k via the passgates PG₅ and PG₆, respectively. Accordingly, data based on the datasignal din_k is written into the target memory cell (C) enabled by theasserted wordline.

The following describes a method of testing an operation of the bitlinedriver 200. The testing of an operation of the bitline driver 200 maybegin in scan shift mode whereby a test vector signal is shifted intothe bitline driver 200. In scan shift mode, the complementary shiftsignals ishift/ishift signal are high/low. Accordingly, the tristateinverters I₁ an I₇ are enabled, and the tristate inverters I₂ and I₈ aredisabled. Thus, a scan path exists from the scan input port sin_k to thescan output port sou_k via the first master-latch 220, first slave-latch230, inverter I₇, second master latch 240, and second slave-latch 250.

During a first half clock cycle when the complementary clock signalsclk/clk are low/high, the test vector signal sin_k is routed from thescan input port sin_k to the input of the inverter I₃ by the tristateinverter I₁ and pass gate PG₁. During a second half clock cycle when thecomplementary clock signals clk/clk are high/low, the first master-latch220 latches the test vector signal sin_k. Also, during the second halfclock cycle, the pass gate PG₂ passes the latched test vector signalsin_k to the input of the inverter I₅ of the first slave-latch 250.

During a third half clock cycle when the complementary clock signalsclk/clk are low/high, the first slave-latch 230 latches the test vectorsignal sin_k. Also, during the third half clock cycle, the pass gate PG₃passes the latched test vector signal sin_k to the input of the inverterI₉ of the second master-latch 240. During a fourth half clock cycle whenthe complementary clock signals clk/clk are high/low, the secondmaster-latch 240 latches the test vector signal sin_k. Also, during thefourth half clock cycle, the pass gate PG₄ passes the latched testvector signal sin_k to the input of the second slave-latch 250.

During a fifth half clock cycle when the complementary clock signalsclk/clk are low/high, the second slave-latch 250 latches the test vectorsignal sin_k to produce it at the scan output port sou_k. Once the testvector signal has been scanned into all of the bitline drivers 0 to n,the bitline driver 200 is operated in scan capture mode where the clocksignal clk is generated at a frequency in accordance with the prescribedtest operation performed on the bitline driver 200. The captured testvector signal is then generated at the outputs of the master-latches 220and 240. Then, the bitline driver 200 is operated again in a scan shiftmode to scan out the captured test vector signal.

Thus, as described above, it takes 2.5 clock cycles for the test vectorsignal sin_k to propagate through the bit line driver 200. Additionally,the bit line driver 200 includes four (4) latches 220, 230, 240, and250. For faster test operation, it would be desirable to reduce thenumber of clock cycles for the test vector signal sin_k to propagatethrough the bitline driver 200. Further, to reduce the integratedcircuit area and power consumption, it would be desirable to reduce thenumber of latches required for the bitline driver 200.

FIG. 3 illustrates a schematic diagram of another exemplary bitlinedriver 300 in accordance with an aspect of the disclosure. The bitlinedriver 300 may be an example of one of the bitline drivers 0 to n ofmemory circuit 100 previously discussed. For instance, the bitline drive300 may be the k^(th) bitline driver of the bitline drivers 0 to n.

In summary, the scan path of bitline driver 300 is split into twoparallel paths: a first path through a latch for the input data signaldin_k, and a second path through a latch for the write mask signalwbt_k. A NOR-gate of a data write circuit merges the two parallel scanpaths into one, and then the merged scan path proceeds to a scan outputlatch.

In this configuration, the propagating of the test vector signal sin_kthrough the bitline driver 300 only requires 1.5 clock cycles, which ismuch faster than the 2.5 clock cycles required by bitline driver 200.Additionally, the bitline driver 300 is implemented with three (3)latches instead of four (4) latches as required by the bitline driver200. This translates into substantial savings in IC area and powerconsumption, as there may be a large number of bitline drivers in amemory circuit.

In particular, the bitline driver 300 includes a multiplexer 310including tristate inverters and I₃, inverter I₂, and pass gates PG₁ andPG₂; a first latch 320 including a pass gate PG₃, inverter I₄ andtristate inverter I₅; a second latch 330 including a pass gate PG₄,inverter I₆ and tristate inverter I₇; and a third latch 340 including apass gate PG₅, inverter I₈ and tristate inverter I₉. The bitline driver300 further a data write circuit 350 including first and secondNOR-gates NG₁ and NG₂, inverters I₁₀ and I₁₁, and pass gates PG₆ andPG₇. The pass gates PG₆ and PG₇ are coupled to complementary bitlinesBL_k/BL_k, respectively. A column of memory cells including acorresponding precharge circuit (both not shown) are coupled to thecomplementary BL_k/BL_k, as previously discussed with reference to FIG.1B.

The tristate inverter I₁ includes an input coupled to an input data portdin_k for receiving a data signal din_k. The tristate inverter I₁ isenabled and disabled based on complementary shift signals ishift/ishift(e.g., enabled if ishift=0 and ishift=1, and disabled if ishift=1 andishift=0). The output of the tristate inverter I₁ is coupled to an inputof the first latch 320 (in particularly, to an input of the pass gatePG₃).

The inverter I₂ includes an input coupled to the scan input port sin_kfor receiving a test vector signal sin_k. The scan input port sin_k iscoupled to the scan output port sou_k−1 of the k^(th)−1 bitline driverif it is not bitline driver 0 or to an external input port if it isbitline driver 0. The output of the inverter I₂ is coupled to respectiveinputs of the pass gates PG₁ and PG₂.

The tristate inverter I₃ includes an input coupled to a write mask portwbt_k for receiving a write mask signal wbt_k. The tristate inverter I₃is enabled and disabled based on complementary shift signalsishift/ishift (e.g., enabled if ishift=0 and ishift=1, and disabled ifishift=1 and ishift=0). The output of the tristate inverter I₃ iscoupled to an input of the second latch 330 (in particular, to an inputthe pass gate PG₄).

The pass gates PG₁ and PG₂ are enabled and disabled based on thecomplementary shift signals shift/ishift (e.g., enabled if ishift=1 andishift=0, and disabled if ishift=0 and ishift=1). The output of the passgate PG₁ is coupled to the input of the first latch 320 (inparticularly, to the input of the pass gate PG₃), and the output of thepass gate PG₂ is coupled to the input of the second latch 330 (inparticularly, to the input of the pass gate PG₄).

The pass gates PG₃ and PG₄ are enabled and disabled based on thecomplementary clock signals clk/clk (e.g., enabled if clk=0 and clk=1,and disabled if clk=1 and clk=0). The output of the pass gate PG₃ of thefirst latch 320 is coupled to the input and output of inverters I₄ andI₅, respectively, and to a first input of NOR-gate NG₂ of the data writecircuit 350. The output of the pass gate PG₄ of the second latch 330 iscoupled to the input and output of inverters I₆ and I₇, respectively.

The first latch 320 is enabled and disabled based on complementary clocksignals clk/clk (e.g., enabled if clk=1 and clk=0, and disabled if clk=0and clk=1). The output of the first latch 320 (at the input and outputof inverters I₄ and I₃, respectively) is coupled to a first input of theNOR-gate NG₁ of the data write circuit 350.

The second latch 330 is enabled and disabled based on complementaryclock signals clk/clk (e.g., enabled if clk=1 and clk=0, and disabled ifclk=0 and clk=1). The output of the second latch 330 (at the input andoutput of inverters I₇ and I₆, respectively) is coupled to respectivesecond inputs of the NOR-gates NG₁ and NG₂ of the data write circuit350.

With regard to the data write circuit 350, the outputs of the NOR-gatesNG₁ and NG₂ are coupled to inputs of inverters I₁₀ and I₁₁,respectively. The outputs of the inverters I₁₀ and I₁₁ are coupled toinputs of pass gates PG₆ and PG₇, respectively. The pass gates PG₆ andPG₇ are controlled by complementary bitline select signals wm/wm. Thepass gates PG₆ and PG₇ are enabled if the signals wm/wm signal arehigh/low, and disabled if the signals wm/wm signal are low/high. Theoutputs of the pass gates PG₆ and PG₇ are coupled to the complementarybitlines BL_k/B_L_k, respectively.

The output of the first NOR-gate NG₁ of the data write circuit 350 iscoupled to an input of the third latch 340 (in particularly, to an inputof the pass gate PG₅). The pass gates PG₅ is enabled and disabled basedon the complementary clock signals clk/clk (e.g., enabled if clk=1 andclk=0, and disabled if clk=0 and clk=1). The output of the pass gate PG₅is coupled to the input and output of inverters I₈ and I₉, respectively.The output of the third latch 340 (at the input and output of invertersI₉ and I₈, respectively) is coupled to the scan output port sou_k of thebitline driver 300. The scan output port sou_k is coupled to the scaninput sin_k+1 of the k^(th)+1 bitline driver if it is not bitline drivern or to an external output port if it is bitline driver n.

The following describes the writing of data to (as well as masking thewriting of data from) a memory cell (C) coupled to complementary bitlineBL_k/BL_k in functional mode. In functional mode, the complementaryshift signals ishift/ishift are logic zero (0) and one (1),respectively. Accordingly, the pass gates PG₁ and PG₂ are disabled ortristated. In functional mode, the third latch 340 serves no function.Additionally, in functional mode, the tristated inverters I₁ and I₃ areenabled.

During a first half clock cycle when the complementary clock signalsclk/clk are low/high, the data signal din_k is routed from the datainput port din_k to the input of the inverter I₄ and the first input ofthe NOR-gate NG₂ by the inverter I₁ and pass gate PG₃. Also, during thefirst half clock cycle, the write mask signal wbt_k is routed from thewrite mask port wbt_k to the input of the inverter I₆ by the tristateinverter I₃ and pass gate PG₄.

During a second half clock cycle when the complementary clock signalsclk/clk is high/low, the pass gates PG₃ and PG₄ are disabled to preventsignal and/or noise at the ports din_k and wbt_k from affecting thelatching of the data signal din_k and write mask signal wbt_k by thefirst and second latches 320 and 330, respectively. Also, during thesecond half clock cycle, the first latch 320 latches the data signaldin_k, and the second latch 230 latches the write mask signal wbt_k.

The latched write mask signal wbt_k is applied to the respective secondinputs of the NOR-gates NG₁ and NG₂ of the data write circuit 350. Theunlatched and inverted data signal data signal din_k is applied to thefirst input of the NOR-gate NG₂, and the latched and non-inverted datasignal din_k is applied to the first input of the NOR-gate NG₁.

If the write mask signal wbt_k is asserted (e.g., at a logic one (1)) tomask the writing of data into a memory cell (C), the NOR-gates NG₁ andNG₂ output logic low states. In response, the inverters I₁₃ and I₁₄generate logic high states. The logic high states are produced on thecomplementary bitlines BL_k/BL_k via the pass gates PG₆ and PG₇, whichare enabled via the bitline select signals wm/wm during a writeoperation. The logic high states on the complementary bitlines BL_k/BL_kprevent the changing of data stored by the memory cell (C) enabled bythe asserted wordline.

If the write mask signal wbt_k is deasserted (e.g., at a logic zero (0))so as not to mask the writing of data into a target memory cell (C), theNOR-gates NG₁ and NG₂ output the inverted and non-inverted data signaldin_k. In response, the inverters I₁₃ and I₁₄ output the non-invertedand inverted data signal din_k. The non-inverted and inverted datasignal din_k are applied to complementary bitlines BL_k/BL_k via thepass gates PG₆ and PG₇, respectively. Accordingly, data based on thedata signal din_k is written into the target memory cell (C) enabled bythe asserted wordline.

The following describes the shifting in of a test vector signal fortesting the operation of the bit line driver 300. In scan shift mode,the complementary shift signals ishift/ishift are high/low,respectively. Accordingly, the pass gates PG₁ and PG₂ are enabled, andthe tristate inverters I₁ and I₃ are disabled or tristated. Thus, twoparallel scan paths exist from the scan input port sin_k to the scanoutput sou_k: The first path traverses pass gate PG₁ and first latch320; the second path traverses pass gate PG₂ and the second latch 330.The NOR-gate NG₁ merges the parallel scan paths into a single path, andcontinues to the scan output port sou_k via the third latch 340.

During a first half clock cycle when the complementary clock signalsclk/clk are low/high, a test vector signal sin_k is routed from the scaninput port sin_k to the input of the inverter I₄ of the first latch 320by the pass gates PG₁ and PG₃. Also, during this first half clock cycle,the test vector signal sin_k is also routed from the scan input portsin_k to the input of the inverter I₆ of the second latch 330 by thepass gates PG₂ and PG₄. During a second half clock cycle when thecomplementary clock signals clk/clk are high/low, the first and secondlatches 320 and 330 latch the test vector signal sin_k.

Accordingly, the NOR-gate NG₁ outputs the test vector signal sin_k(albeit, inverted). Also, during the second half clock cycle, the passgate PG₅ passes the inverted test vector signal sin_k to the input ofinverter I₈ of the third latch 340. During the third half clock cyclewhen the complementary clock signals clk/clk are low/high, the thirdlatch 340 latches the test vector signal sin_k to produce it at the scanoutput port sou_k.

Thus, as described above, it takes 1.5 clock cycles for the test vectorsignal sin_k to propagate through the bitline driver 300, instead of 2.5clock cycles required by the bitline driver 200. Thus, the bitlinedriver 300 is able to propagate a test vector signal much faster thanbitline driver 200. Additionally, the bitline driver 300 has only three(3) latches, whereas bitline driver 200 has four (4) latches. Thistranslates to substantial savings in IC area and power consumption asthe IC may include many bitline drivers depending on the size of thecorresponding memory array.

FIG. 4 illustrates a schematic diagram of another exemplary bitlinedriver 400 in accordance with another aspect of the disclosure. Thebitline driver 400 may be an example of one of the bitline drivers 0 ton of memory circuit 100 previously discussed. For instance, the bitlinedrive 400 may be the k^(th) bitline driver of the bitline drivers 0 ton.

In particular, the bitline driver 400 includes a multiplexer 410(generally, a gating device or circuit) including inverters I₁ and I₂,and NOR-gates NG₁, NG₂, and NG₃; a master-latch 420 including NG₄, NG₅,NG₆, NG₇, and NG₈; a slave-latch 430 including NOR-gates NG₉, NG₁₀,NG₁₁, NG₁₂, and NG₁₃; and a data write circuit 440 including invertersI₃ and I₄, pass gates PG₁ and PG₂.

The NOR-gates NG₁, NG₂, NG₄, NG₅, NG₆, NG₇, NG₈, NG₁₁, NG₁₂, and NG₁₃are three-input NOR-gates, and the NOR-gates NG₃, NG₉, and NG₁₀ aretwo-input NOR-gates. For description purposes, the inputs of eachNOR-gate are referred to below in consecutive order beginning with“first input” for the upper input, “second input” for the middle inputof a three-input NOR-gate and lower input of a two-input NOR-gate, and“third input” for the lower input of a three-input NOR-gate.

The data input port din_k is coupled to an input of the inverter I₁ anda first input of NOR-gate NG₁. The output of the inverter I₁ is coupledto a third input of NOR-gate NG₂. The write mask port wbt_k is coupledto the respective second inputs of NOR-gates NG₁ and NG₂. The scan shiftsignal ishift is applied to first and third inputs of NOR-gates NG₁ andNG₂, respectively. The scan input port sin_k is coupled to an input ofthe inverter I₂. The output of the inverter I₂ is coupled to a firstinput of the NOR-gate NG₃. The complementary shift signal ishift isapplied to a second input of the NOR-gate NG₃.

The output of the NOR-gate NG₁ is coupled to a second input of theNOR-gate NG₄. The output of the NOR-gate NG₂ is coupled to a secondinput of the NOR-gate NG₅. The output of the NOR-gate NG₃ is coupled tofirst and third inputs of NOR-gates NG₄ and NG₅, respectively. The clocksignal clk is applied to the third and first inputs of NOR-gates NG₄ andNG₅, respectively.

The NOR-gates NG₆ and NG₇ are cross-coupled. That is, the output ofNOR-gate NG₆ is coupled to a first input of NOR-gate NG₇, and the outputof NOR-gate NG₇ is coupled to a third input of NOR-gate NG₆. The outputof NOR-gate NG₄ is coupled to a second input of NOR-gate NG₆. The outputof NOR-gate NG₅ is coupled to a second input of NOR-gate NG₇. Theoutputs of NOR-gates NG₆ and NG₇ are coupled to second and first inputsof NOR-gate NG₈, respectively. The complementary clock signal clk isapplied to a third input of NOR-gate NG₈. The output of NOR-gate NG₈ iscoupled to first and third inputs of NOR-gates NG₆ and NG₇,respectively.

The output of NOR-gate NG₆ is also coupled to a first input of NOR-gateNG₉ and to an input of inverter I₃. The output of NOR-gate NG₇ iscoupled to a second input of NOR-gate NG₁₀ and to an input of inverterI₄. The complementary clock signal clk is applied to second and firstinputs of NOR-gates NG₉ and NG₁₀, respectively.

The NOR-gates NG₁₁ and NG₁₂ are cross-coupled. That is, the output ofNOR-gate NG₁₁ is coupled to a first input of NOR-gate NG₁₂, and theoutput of NOR-gate NG₁₂ is coupled to a third input of NOR-gate NG₁₁.The output of NOR-gate NG₉ is coupled to a second input of NOR-gateNG₁₁. The output of NOR-gate NG₁₀ is coupled to a second input ofNOR-gate NG₁₂. The outputs of NOR-gates NG₁₁ and NG₁₂ are coupled tosecond and first inputs of NOR-gate NG₁₃, respectively. The clock signalclk is applied to a third input of NOR-gate NG₁₃. The output of NOR-gateNG₁₃ is coupled to first and third inputs of NOR-gates NG₁₁ and NG₁₂,respectively. The scan output port sou_k for the bitline driver 300 iscoupled to the output of the NOR-gate NG₁₂.

The outputs of the inverters I₃ and I₄ are coupled to inputs of passgates PG₁ and PG₂, respectively. The outputs of the pass gates PG₁ andPG₂ are coupled to the complementary bitlines BL_k/BL_k, respectively. Acolumn of memory cells including a corresponding precharge circuit (bothnot shown) are coupled to the complementary BL_k/BL_k, as previouslydiscussed with reference to FIG. 1B.

The following describes the writing of data to (as well as masking thewriting of data from) a memory cell (C) coupled to complementary bitlineBL_k/BL_k in functional mode. In functional mode, the complementaryshift signals ishift/ishift are logic zero (0) and one (1),respectively. Also, in functional mode, the slave-latch 430 does notserve a function.

In this example, the write mask signal wbt_k is deasserted (e.g., at alogic zero (0)) so as not to mask the writing of data into the targetmemory cell (C). If the write mask signal wbt_k were asserted (e.g., ata logic one (1)), the master-latch 420 latches two logic low signals atthe outputs of NOR-gates NG₆ and NG₇. In response, the inverters I₃ andI₄ produce logic high signals on the complementary bitlines BL_k/BL_kvia the pass gates PG₁ and PG₂ enabled by the complementary bitlineselect signals wm/wm. The logic high signals on the bitlines BL_k/BL_kprevent the writing of data to a memory cell selected by a correspondingasserted wordline.

With the ishift and write mask signals being deasserted, the multiplexer410 outputs the data signal din_k. That is, the ishift and write masksignals being logic zeros (Os) and being applied to two inputs of thethree-input NOR-gates NG₁ and NG₂ essentially enable the gates to outputinverted and non-inverted data signal din_k, respectively. Further, thecomplementary shift signal ishift, being a logic one (1) in functionalmode, causes the NOR-gate NG₃ to output a logic zero (0) so as to enablethe NOR-gates NG₄ and NG₅ from the scan input perspective.

During a first half clock cycle when the complementary clock signalsclk/clk are low/high, the NOR-gates NG₄ and NG₅ output the non-invertedand inverted data signal din_k, respectively. Also, during the firsthalf clock cycle, the NOR-gate NG₈ generates a logic zero (0) to enablethe cross-coupled NOR-gates NG₆ and NG₇ to output inverted andnon-inverted data signal din_k, respectively.

During a second half clock cycle when the complementary clock signalsclk/clk are high/low, respectively, the clock signal clk disables theNOR-gates NG₄ and NG₅ to prevent signal and/or noise at the data inputport din_k from affecting the data latched by the master-latch 420. Thecomplementary clock signal clk causes the NOR-gate NG₈ to output a logicone (1) so that the cross-coupled NOR-gates NG₆ and NG₇ latch theinverted and non-inverted data signal din_k at the outputs of theNOR-gates, respectively.

In response to the latched inverted and non-inverted data signal din_k,the inverters I₃ and I₄ generate non-inverted and inverted data signaldin_k, respectively. Based on the bitline select signals wm/wm beingasserted (e.g., at logic high and low, respectively), the pass gates PG₁and PG₂ pass the non-inverted and inverted data signal din_k to thecomplementary bitlines BL_k/BL_k, respectively. This causes the writingdata into the target memory cell (C) based on the data signal din_k.

In scan shift mode, the complementary shift signals ishift/ishift arelogic one (1) and logic zero (0), respectively. The signal ishift beinga logic one (1) effectively disables the NOR-gates NG₁ and NG₂ so thatthey both output logic zeros (Os). The inverter I₂ generates an invertedtest vector signal sin_k. The complementary signal ishift being a logiczero (0) causes the NOR-gate NG₃ to output the non-inverted test vectorsignal sin_k.

During a first half clock cycle, the complementary clock signals clk/clkare logic low and high, respectively. The clock signal clk being lowcauses the NOR-gates NG₄ and NG₅ to both output the inverted test vectorsignal sin_k. The complementary clock signal clk being high causes theNOR-gate NG₈ to output a logic low. This causes the cross-coupledNOR-gates NG₆ and NG₇ to output the non-inverted test vector signalsin_k.

During a second half clock cycle, the complementary clock signalsclk/clk are logic high and low, respectively. The clock signal clk beinghigh disables the NOR-gates NG₄ and NG₅ to prevent signal and/or noiseat the scan input port sin_k from affecting the test vector signal sin_klatched by the master-latch 420. The complementary clock signal clkbeing low causes the NOR-gate NG₈ to output a logic one (1) so that thecross-coupled NOR-gates NG₆ and NG₇ latch the non-inverted test vectorsignal sin_k. The complementary clock signal clk being low also causesthe NOR-gates NG₉ and NG₁₀ to output the inverted test vector signalsin_k.

During a third half clock cycle, the complementary clock signals clk/clkare logic low and high, respectively. The complementary clock signal clkbeing high disables the NOR-gates NG₉ and NG₁₀ to prevent the output ofthe master-latch 420 from affecting the data latched by the slave-latch430. The clock signal clk being low causes the NOR-gate NG₁₃ to output alogic one (1) so that the cross-coupled NOR-gates NG_(ii) and NG₁₂ latchthe test vector signal sin_k and provide it to the scan output portsou_k.

Thus, as described above, it takes 1.5 clock cycles for the test vectorsignal sin_k to propagate through the bitline driver 400, instead of 2.5clock cycles required by the bitline driver 200. Thus, the bitlinedriver 400 is able to propagate a test vector signal much faster thanbitline driver 200. Additionally, the bitline driver 400 has only two(2) latches, whereas bitline driver 200 has four (4) latches. Thistranslates to substantial savings in IC area and power consumption asthe IC may include many bitline drivers depending on the size of thecorresponding memory array.

FIG. 5 illustrates a flow diagram of an exemplary method 500 ofoperating a bitline driver in accordance with another aspect of thedisclosure.

The method 500 includes latching a data signal at a first node inresponse to a first state of a clock signal if a scan shift signal isdeasserted (block 510). An example of a means for latching a data signalat a first node in response to a first state of a clock signal if a scanshift signal is deasserted includes tristate inverter I₁, pass gate PG₁,and the latch 320 of bitline driver 300.

The method 500 further includes latching a test vector signal at thefirst node in response to the first state of the clock signal if thescan shift signal is asserted (block 520). An example of a means forlatching a test vector signal at the first node in response to the firststate of the clock signal if the scan shift signal is asserted includestristate inverter I₁, pass gate PG₁, and the latch 320 of bitline driver300.

The method 500 further includes latching a write mask signal at a secondnode in response to the first state of the clock signal if the scanshift signal is deasserted (block 530). An example of a means forlatching a write mask signal at a second node in response to the firststate of the clock signal if the scan shift signal is deassertedincludes tristate inverter I₃, pass gate PG₂, and the latch 330 ofbitline driver 300.

The method 500 further includes latching the test vector signal at thesecond node in response to the first state of the clock signal if thescan shift signal is asserted (block 540). An example of a means forlatching the test vector signal at the second node in response to thefirst state of the clock signal if the scan shift signal is assertedincludes tristate inverter I₃, pass gate PG₂, and the latch 330 ofbitline driver 300.

FIG. 6 illustrates a flow diagram of an exemplary method 600 ofoperating a bitline driver in accordance with another aspect of thedisclosure.

The method 600 includes latching a data signal at a first node inresponse to a first state of a clock signal if a write mask signal and ascan shift signal are deasserted (block 610). An example of a means forlatching a data signal at a first node in response to a first state of aclock signal if a write mask signal and a scan shift signal aredeasserted includes the master-latch 420 of bitline driver 400.

The method 600 further includes latching a test vector signal at thefirst node in response to the first state of the clock signal if thescan shift signal is asserted (block 620). An example of a means forlatching a test vector signal at the first node in response to the firststate of the clock signal if the scan shift signal is asserted includesthe master-latch 420 of bitline driver 400.

The method 600 further includes latching the test vector signal at asecond node in response to a second state of the clock signal if thescan shift signal is asserted (block 630). An example of a means forlatching the test vector signal at a second node in response to a secondstate of the clock signal if the scan shift signal is asserted includesthe slave-latch 430 of bitline driver 400.

The previous description of the disclosure is provided to enable anyperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the spirit or scopeof the disclosure. Thus, the disclosure is not intended to be limited tothe examples described herein but is to be accorded the widest scopeconsistent with the principles and novel features disclosed herein.

What is claimed is:
 1. An apparatus, comprising: a first latchconfigured to: latch a data signal in response to a first state of aclock signal if a scan shift signal is deasserted; and latch a testvector signal in response to the first state of the clock signal if thescan shift signal is asserted; and a second latch configured to: latch awrite mask signal in response to the first state of the clock signal ifthe scan shift signal is deasserted; and latch the test vector signal inresponse to the first state of the clock signal if the scan shift signalis asserted.
 2. The apparatus of claim 1, further comprising a gatingcircuit configured to: route the test vector signal from a scan inputport to the first and second latches in response to the scan shiftsignal being asserted; and prevent the routing of the test vector signalfrom the scan input port to the first and second latches in response tothe scan shift signal being deasserted.
 3. The apparatus of claim 2,wherein the gating circuit comprises: a first pass gate coupled betweenthe scan input port and the first latch, wherein the first pass gateturns on in response to the scan shift signal being asserted, and turnsoff in response to the scan shift signal being deasserted; and a secondpass gate coupled between the scan input port and the second latch,wherein the second pass gate turns on in response to the scan shiftsignal being asserted, and turns off in response to the scan shiftsignal being deasserted.
 4. The apparatus of claim 1, further comprisinga gating device coupled between a data input port for receiving the datasignal and an input of the first latch, wherein the gating device isconfigured to: generate the data signal at an output of the gatingdevice in response to the scan shift signal being deasserted; andtristate the output in response to the scan shift signal being asserted.5. The apparatus of claim 1, further comprising a gating device coupledbetween a write mask input port for receiving the write mask signal andan input of the second latch, wherein the gating device is configuredto: generate the write mask signal at an output of the gating device inresponse to the scan shift signal being deasserted; and tristate theoutput in response to the scan shift signal being asserted.
 6. Theapparatus of claim 1, wherein the first latch comprises: a firstinverter; a pass gate configured to: pass the data signal or the testvector signal from an input of the pass gate to the first inverter inresponse to a second state of the clock signal; decouple the input fromthe first inverter in response to the first state of the clock signal; asecond inverter configured to: be cross-coupled with the first inverterto latch the data signal or the test vector signal in response to thefirst state of the clock signal; and not be cross-coupled with the firstinverter in response to the second state of the clock signal.
 7. Theapparatus of claim 1, wherein the second latch comprises: a firstinverter; and a pass gate configured to: pass the write mask signal orthe test vector signal from an input of the pass gate to the firstinverter in response to a second state of the clock signal; decouple theinput from the first inverter in response to the first state of theclock signal; a second inverter configured to: be cross-coupled with thefirst inverter to latch the write mask signal or the test vector signalin response to the first state of the clock signal; and not becross-coupled with the first inverter in response to the second state ofthe clock signal.
 8. The apparatus of claim 1, further comprising athird latch configured to latch the test vector signal in response to asecond state of the clock signal if the scan shift signal is asserted,wherein the latched test vector signal is produced at a scan outputport.
 9. The apparatus of claim 1, wherein the third latch comprises: afirst inverter; a pass gate configured to: pass the test vector signalfrom an input of the pass gate to the first inverter in response to thefirst state of the clock signal; decouple the input from the firstinverter in response to the second state of the clock signal; a secondinverter configured to: be cross-coupled with the first inverter tolatch the test vector signal in response to the second state of theclock signal; and not be cross-coupled with the first inverter inresponse to the first state of the clock signal.
 10. The apparatus ofclaim 1, further comprising a data write circuit configured to writedata to a memory cell coupled to complementary bitlines based on thedata signal if the write mask signal is deasserted.
 11. The apparatus ofclaim 10, wherein the data write circuit comprises: a first OR-gate orfirst NOR-gate including a first input configured to receive the latcheddata signal from the first latch, a second input configured to receivethe latched write mask signal from the second latch, and an outputcoupled to one of the complementary bitlines; and a second OR-gate orsecond NOR-gate including a first input configured to receive the datasignal from the first latch, a second input configured to receive thelatched write mask signal from the second latch, and an output coupledto the other of the complementary bitlines.
 12. The apparatus of claim11, wherein the data write circuit comprises: a first pass gateconfigured to route the data signal from the first OR-gate or the firstNOR-gate to the one of the complementary bitlines in response to anasserted state of a bitline select signal; and a second pass gateconfigured to route the data signal from the second OR-gate or thesecond NOR-gate to the other of the complementary bitlines in responseto the asserted state of the bitline select signal.
 13. The apparatus ofclaim 11, further comprising a third latch configured to latch the testvector signal in response to a second state of the clock signal if thescan shift signal is asserted, wherein the latched test vector signal isproduced at a scan output port, and wherein the first OR-gate or firstNOR-gate is coupled between the first latch and the third latch.
 14. Amethod, comprising: latching a data signal at a first node in responseto a first state of a clock signal if a scan shift signal is deasserted;latching a test vector signal at the first node in response to the firststate of the clock signal if the scan shift signal is asserted; latchinga write mask signal at a second node in response to the first state ofthe clock signal if the scan shift signal is deasserted; and latchingthe test vector signal at the second node in response to the first stateof the clock signal if the scan shift signal is asserted.
 15. The methodof claim 14, further comprising: routing the test vector signal from ascan input port to first and second latches for latching the test vectorsignal at the first and second nodes, respectively, in response to thescan shift signal being asserted; and decoupling the scan input portfrom the first and second latches in response to the scan shift signalbeing deasserted.
 16. The method of claim 14, further comprising:routing the data signal from a data input port to a latch for latchingthe data signal at the first node in response to the scan shift signalbeing deasserted; and decoupling the data input port from the latch inresponse to the scan shift signal being asserted.
 17. The method ofclaim 14, further comprising: routing the write mask signal from a writemask input port to a latch for latching the write mask signal at thefirst node in response to the scan shift signal being deasserted; anddecoupling the write mask input port from the latch in response to thescan shift signal being asserted.
 18. The method of claim 14, furthercomprising: latching the test vector signal at a third node in responseto a second state of the clock signal if the scan shift signal isasserted; and routing the latched test vector to a scan output port. 19.The method of claim 14, further comprising writing data to a memory cellbased on the data signal if the write mask signal is deasserted.
 20. Themethod of claim 14, further comprising masking a writing of data to amemory cell if the write mask signal is asserted.